Binary counter

A binary counter is a sequential circuit whose output bits represent a count in binary. It remembers its current state and changes that state when a clock input triggers it.

In an up-counter, the count increases by one on each active clock edge. In a down-counter, it decreases by one. If the counter has an up/down control, that input selects which direction the count follows.

Binary counter states and wraparound

A counter with $$k$$ output bits can represent $$2^k$$ different states, from zero to $$2^k - 1$$. After an up-counter reaches its largest value, the next active clock edge makes it wrap around to zero. A down-counter wraps from zero to its largest value.

For example, a three-bit up-counter has $$2^3 = 8$$ states. Its outputs follow this sequence:

$$000, 001, 010, 011, 100, 101, 110, 111, 000, \ldots$$

Each group of bits shows the current count. Several bits can change on the same count: for example, the transition from $$011$$ to $$100$$ changes all three bits. A three-bit down-counter follows the sequence in the opposite direction, wrapping from $$000$$ to $$111$$.

Resetting a binary counter

A reset input sets the counter to its initial state, normally zero. The output bits then show that initial count.

BCD counter

A binary-coded decimal (BCD) counter represents one decimal digit using four output bits. The bits show the digit’s value in binary: from left to right, their place values are $$8$$, $$4$$, $$2$$ and $$1$$. For example, $$0101$$ represents $$5$$ and $$1001$$ represents $$9$$.

BCD counting sequence

The normal sequence uses only the four-bit patterns for decimal digits $$0$$ to $$9$$:

• Digits $$0$$ to $$4$$: $$0000$$, $$0001$$, $$0010$$, $$0011$$, $$0100$$
• Digits $$5$$ to $$9$$: $$0101$$, $$0110$$, $$0111$$, $$1000$$, $$1001$$

The six remaining four-bit patterns, from $$1010$$ to $$1111$$, are not part of the normal BCD counting sequence.

An up-counter advances through the sequence and returns from $$1001$$ to $$0000$$ after nine. A down-counter moves through the sequence in reverse and returns from $$0000$$ to $$1001$$ after zero.

BCD counter inputs and outputs

The clock triggers the counter to change its count. The reset input normally returns the output to $$0000$$. Where an up/down input is provided, it selects the direction of counting. At any point, the four output bits indicate the current decimal digit in BCD.

Johnson counter

A Johnson counter stores a pattern of bits in a chain of stages. On each active clock edge, the pattern moves along the chain, while a new bit enters the first stage. That new bit is the inverted output of the last stage: a stored $$0$$ is fed back as $$1$$, and a stored $$1$$ is fed back as $$0$$.

All stages update on the same active clock edge. Each stage after the first takes the previous value of the stage before it; the first takes the inverted previous value of the last stage. This feedback makes the counter cycle through a repeating sequence of patterns.

Johnson counter sequence

A reset establishes a suitable starting pattern, such as all zeros. For a three-stage counter, write the first stage on the left and shift towards the right. Starting from $$000$$, the sequence is:

For example, at $$110$$ the last stage contains $$0$$, so its inverted value, $$1$$, enters the first stage on the next clock edge. The other values shift right, producing $$111$$. From $$111$$, the last stage contains $$1$$, so a $$0$$ enters and the next pattern is $$011$$.

There are six distinct patterns before the sequence repeats. In general, starting from a suitable reset state, a Johnson counter with $$k$$ stages cycles through $$2k$$ distinct states.

The stage outputs show which pattern the counter currently holds. They are not generally a conventional binary representation of the count: for example, the first pattern after $$000$$ is $$100$$, not $$001$$. A reversible design may include a direction control, but this is not a feature of every Johnson counter.

Modulo-n counter design

A modulo-$$n$$ counter repeats a sequence of $$n$$ states. An up-counter that starts at zero normally follows the sequence $$0, 1, 2, \ldots, n-1$$, then returns to zero.

A basic counter can be made to follow this shorter sequence by connecting logic gates to its outputs. The gates detect a selected output pattern and use it to assert the counter’s reset input. The pattern to detect depends on when the reset takes effect.

The counter must have enough states to represent the required sequence. A counter with $$k$$ binary output bits has $$2^k$$ possible states, so it must satisfy $$2^k \geq n$$. If the required sequence uses all of those states, the counter can normally return to zero by wrapping around after its highest count.

Reset timing in a modulo-n counter

With an asynchronous reset, the counter resets without waiting for a clock edge. The detection logic can therefore detect the first unwanted count, $$n$$, and immediately assert reset. The count $$n$$ may appear briefly while the logic and reset respond, but it is not a normal sustained state in the sequence. This method requires the counter to be able to represent $$n$$ as well as the required states.

With a synchronous reset, reset takes effect only at an active clock edge. The logic must assert reset while the counter is at $$n-1$$, so that the next active clock edge takes it to zero instead of $$n$$.

Modulo-6 design example

A three-bit counter has eight possible states, enough for a modulo-6 sequence. Its normal count is $$0$$ to $$5$$, or $$000$$ to $$101$$ in binary.

• For an asynchronous reset, detect $$110$$, the binary pattern for $$6$$. When it appears, reset returns the counter to $$000$$.
• For a synchronous reset, detect $$101$$, the pattern for $$5$$. Reset is then asserted before the next active clock edge, which returns the counter to $$000$$.

The detection gates must recognise the intended pattern. For example, to detect $$110$$ exactly, an AND gate can combine the two output bits that must be high with an inverted version of the bit that must be low.

The reset signal must also have the correct polarity. If reset is active-high, it is asserted by a high signal; if it is active-low, it is asserted by a low signal. An inverter can change the detection signal’s polarity when needed.